Configuration Options for 18F65J10

   Background Debugger Enable:
     DEBUG = ON           Enabled
     DEBUG = OFF          Disabled

   Extended Instruction Set Enable:
     XINST = OFF          Disabled
     XINST = ON           Enabled

   Stack Overflow Reset:
     STVREN = OFF         Disabled
     STVREN = ON          Enabled

   Watchdog Timer:
     WDTEN = OFF          Disabled
     WDTEN = ON           Enabled

   Code Protection:
     CP0 = ON             Enabled
     CP0 = OFF            Disabled

   Fail Safe Clock Monitor:
     FCMEN = OFF          Disabled
     FCMEN = ON           Enabled

   Internal/External Switch Over:
     IESO = OFF           Disabled
     IESO = ON            Enabled

   Default/Reset System Clock Select:
     FOSC2 = OFF          When SCS1:SCS0 = 00, INTRC is the clock source
     FOSC2 = ON           When SCS1:SCS0 = 00, FOSC1:FOSC0 sets the clock source

   Oscillator Selection bits:
     FOSC = HS            HS oscillator
     FOSC = HSPLL         HS oscillator, Software Controlled PLL
     FOSC = EC            External Clock
     FOSC = ECPLL         External Clock, Software Controlled PLL

   Watchdog Postscaler:
     WDTPS = 1            1:1
     WDTPS = 2            1:2
     WDTPS = 4            1:4
     WDTPS = 8            1:8
     WDTPS = 16           1:16
     WDTPS = 32           1:32
     WDTPS = 64           1:64
     WDTPS = 128          1:128
     WDTPS = 256          1:256
     WDTPS = 512          1:512
     WDTPS = 1024         1:1024
     WDTPS = 2048         1:2048
     WDTPS = 4096         1:4096
     WDTPS = 8192         1:8192
     WDTPS = 16384        1:16384
     WDTPS = 32768        1:32768

   CCP2 Mux:
     CCP2MX = ALTERNATE   Muxed with RB3
     CCP2MX = DEFAULT     Muxed with RC1