Configuration Options for 18F2321
Oscillator Selection:
OSC = LP LP Oscillator
OSC = XT XT Oscillator
OSC = HS HS Oscillator
OSC = EC External Clock on OSC1, OSC2 as Fosc/4
OSC = ECIO External Clock on OSC1, OSC2 as RA6
OSC = HSPLL HS + PLL
OSC = RCIO External RC on OSC1, OSC2 as RA6
OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6
OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as Fosc/4
OSC = RC External RC on OSC1, OSC2 as Fosc/4
Fail Safe Clock Monitor:
FSCM = OFF Disabled
FSCM = ON Enabled
Internal External Osc. Switch Over:
IESO = OFF Disabled
IESO = ON Enabled
Power Up Timer:
PWRT = ON Enabled
PWRT = OFF Disabled
Brown Out Reset:
BOR = OFF Disabled Always
BOR = SOFT Enabled by SBOREN
BOR = NOSLP Enabled except in SLEEP
BOR = ON Enabled Always
Brown Out Voltage:
BORV = 45 4.5V
BORV = 42 4.2V
BORV = 27 2.7V
BORV = 20 2.0V
Watchdog Timer:
WDT = OFF Disabled
WDT = ON Enabled
Watchdog Postscaler:
WDTPS = 1 1: 1
WDTPS = 2 1: 2
WDTPS = 4 1: 4
WDTPS = 8 1: 8
WDTPS = 16 1: 16
WDTPS = 32 1: 32
WDTPS = 64 1: 64
WDTPS = 128 1: 128
WDTPS = 256 1: 256
WDTPS = 512 1: 512
WDTPS = 1024 1: 1024
WDTPS = 2048 1: 2048
WDTPS = 4096 1: 4096
WDTPS = 8192 1: 8192
WDTPS = 16384 1:16384
WDTPS = 32768 1:32768
MCLR Enable:
MCLRE = OFF Disabled
MCLRE = ON Enabled
T1 Oscillator Enable:
LPT1OSC = HIGH High Power - High Noise Immunity
LPT1OSC = LOW Low Power - Low Noise Immunity
Port B A/D Enable:
PBAD = DIG PORTB<4:0> digital on RESET
PBAD = ANA PORTB<4:0> analog on RESET
CCP2 Mux:
CCP2MX = RB3 Muxed with RB3
CCP2MX = RC1 Muxed with RC1
Stack Overflow Reset:
STVREN = OFF Disabled
STVREN = ON Enabled
Low Voltage ICSP:
LVP = OFF Disabled
LVP = ON Enabled
ICD Port Enable:
ICPORT = OFF Disabled
ICPORT = ON Enabled
Boot Block Size:
BBSIZ = BB256 256 Word
BBSIZ = BB512 512 Word
BBSIZ = BB1K 1024 Word
XINST Enable:
XINST = OFF Disabled
XINST = ON Enabled
Background Debugger Enable:
DEBUG = ON Enabled
DEBUG = OFF Disabled
Code Protect - Block 0:
CP0 = ON Protected
CP0 = OFF Open
Code Protect - Block 1:
CP1 = ON Protected
CP1 = OFF Open
Code Protect - Boot Block:
CPB = ON Protected
CPB = OFF Open
Code Protect - Data EEPROM:
CPD = ON Protected
CPD = OFF Open
Table Write - Block 0:
WRT0 = ON Protected
WRT0 = OFF Open
Table Write - Block 1:
WRT1 = ON Protected
WRT1 = OFF Open
Table Write - Configuration Register:
WRTC = ON Protected
WRTC = OFF Open
Table Write - Boot Block :
WRTB = ON Protected
WRTB = OFF Open
Table Write - Data EEPROM:
WRTD = ON Protected
WRTD = OFF Open
External Block Table Read - Block 0:
EBTR0 = ON Protected
EBTR0 = OFF Open
External Block Table Read - Block 1:
EBTR1 = ON Protected
EBTR1 = OFF Open
External Block Table Read - Boot Block:
EBTRB = ON Protected
EBTRB = OFF Open